The present invention generally relates to computer system clocks, and more particularly to a method and apparatus for generating an output clock signal, which is synchronized with a reference clock signal with the aid of a phase-locked loop (PLL).
Modern digital electronic computers perform a number of routine operations which are controlled by separate clock signals. However, the clock signals must be synchronized (though not necessarily completely matched in all computer systems) at predetermined locations in order for proper functioning of the computer. When simultaneously generated, these separate clock signals do not often arrive at a chosen destination in synchronism, due to variations in circuit propagation delay, and other things which may affect the propagation delay of the individual clock signals. This effect may be more pronounced in systems which use circuits with more than one logic family (such as Emitter-coupled logic (ECL), Transistor-transistor logic (TTL), and Complementary metal-oxide-semiconductor (CMOS), for example).
Thus, there is a need to synchronize (i.e., "de-skew", or match rising edges) output clocks with a reference clock. In order to adjust the output clock signal to match that of the reference clock signal, prior art PLLs typically include a phase detector, a low-pass filter in a forward signal path, and a voltage-controlled oscillator (VCO) in a feedback path. However, precision is often not as high as is desired, since the stability of VCOs is affected by temperature and supply voltage changes.